Structured training, taught by the engineers who do the R&D work

Alongside our engineering practice and NanoGyan, we run modular training for individuals — students and working professionals — across the same six domains, from foundations to advanced levels. A secondary offering, not the core business.

RTL Design

Digital logic to SoC-level RTL — Verilog, SystemVerilog, RISC-V

RTL design is where a chip's functionality is described in code. This track takes you from digital logic fundamentals through to designing and integrating SoC-level IP — the same progression used in our own R&D work.

Foundations

  • Digital logic design fundamentals
  • Verilog HDL — syntax, modules, testbenches
  • Combinational & sequential circuit design
  • SystemVerilog for design

Intermediate

  • RISC-V instruction set architecture
  • 5-stage pipeline processor design
  • Memory & bus interface design
  • Synthesisable coding guidelines

Advanced — Basic IP to SoC

  • Basic IP design (FIFOs, controllers, arbiters)
  • Sub-system design & integration
  • SoC-level RTL design

Design Verification

SystemVerilog, UVM, coverage closure — IP to SoC verification

Verification ensures a design behaves correctly before it ever reaches silicon. This track builds verification engineers from SystemVerilog fundamentals through to full SoC-level verification using industry-standard methodology.

Foundations

  • SystemVerilog for verification
  • Verification planning & test strategy
  • Assertion-based verification (SVA)
  • Linting & code coverage basics

Intermediate

  • Universal Verification Methodology (UVM)
  • Constrained random verification
  • Functional coverage & coverage closure
  • Scoreboards, sequencers & drivers

Advanced — IP to SoC Verification

  • IP-level verification environments
  • Sub-system verification
  • SoC-level verification & integration
  • Formal verification fundamentals

Physical Design

Floorplanning to sign-off — the full RTL-to-GDSII flow

Physical design turns a verified RTL design into a manufacturable layout. This track covers the complete RTL-to-GDSII flow.

Foundations

  • ASIC design flow overview
  • Standard cell design basics
  • Logic synthesis fundamentals
  • Design constraints (SDC) basics

Intermediate

  • Floorplanning & power planning
  • Placement & clock tree synthesis
  • Routing fundamentals
  • Static timing analysis (STA) basics

Advanced — Sign-off

  • Timing closure & signal integrity
  • Physical verification (DRC/LVS)
  • Sign-off readiness

Custom Layout & Analog

Full-custom layout, analog & mixed-signal design, physical verification

For those heading into analog and mixed-signal design roles. This track focuses on hands-on layout work, building toward production-quality cell and block layouts.

Foundations

  • CMOS device fundamentals
  • Custom layout fundamentals
  • Design rule basics

Advanced

  • Advanced layout: logic & sequential cells
  • Analog & mixed-signal layout
  • Physical verification — DRC & LVS

Design for Test (DFT)

Scan insertion, ATPG, MBIST and test compression

DFT ensures manufactured chips can be efficiently tested for defects. This track covers the core techniques used to make a design testable at scale.

Core topics

  • DFT fundamentals & test economics
  • Scan insertion & scan chain design
  • Automatic test pattern generation (ATPG)
  • Memory BIST (MBIST)
  • Test compression techniques

Embedded Systems & Edge AI

Microcontrollers, RTOS, protocols, and on-device inference

From microcontroller fundamentals to running AI models at the edge. This track builds engineers who can bridge classic firmware development with modern on-device AI workloads.

Foundations

  • C/C++ for microcontrollers
  • Embedded programming with Arduino
  • GPIO, timers & interrupts
  • ADC & sensor interfacing

Intermediate

  • ARM Cortex-M architecture
  • Real-time operating systems (RTOS)
  • UART, SPI & I2C protocols

Advanced — Edge AI

  • On-device inference (Jetson-class platforms)
  • IoT connectivity protocols
  • Bluetooth Low Energy (BLE) integration

Looking for something more immersive?

NanoGyan brings this same curriculum, real EDA tools, and our own engineers directly onto college campuses — our college partnership model, not a standalone individual course.

Learn about NanoGyan

Not sure which track is right for you?

Tell us your background and what you're aiming for — we'll point you to the right starting level.

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